512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
2
A8
3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
NC
4
5
6
Standard Pinout
Top View
WE#
7
V
8
DD
NC
NC
A15
A12
A7
9
V
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
A6
A1
A5
A2
A4
A3
301 ILL F01.2
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
NC
NC
A15
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
WE#
NC
2
3
4
A14
A13
A8
5
32-pin
PDIP
A6
6
A5
7
A9
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
A3
9
A2
10
11
12
13
14
15
16
A1
A0
DQ0
DQ1
DQ2
V
SS
301 ILL F02.2
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
TABLE 2: PIN DESCRIPTION
Symbol
A15-A7
A6-A0
Pin Name
Functions
Row Address Inputs
Column Address Inputs
To provide memory addresses. Row addresses define a page for a Write cycle.
Column Addresses are toggled to load page data
DQ7-DQ0 Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide: 5.0V supply (±10%) for SST29EE512
3.0V supply (3.0-3.6V) for SST29LE512
2.7V supply (2.7-3.6V) for SST29VE512
VSS
NC
Ground
No Connection
Unconnected pins.
T2.1 301
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01 301
5
SST [ SILICON STORAGE TECHNOLOGY, INC ]
