2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
SRAM Operation
With BES# low and BEF# high, the SST31LF021/021E
operate as a 128K x8 or 32K x8 CMOS SRAM, with fully
static operation requiring no external clocks or timing
strobes. The SRAM is mapped into the first 128 KByte
address space of the device. Read and Write cycle times
are equal.
The SST31LF021/021E devices are suited for applications
that use both nonvolatile flash memory and volatile SRAM
memory to store code or data. For all system applications,
the SST31LF021/021E devices significantly improve per-
formance and reliability, while lowering power consumption,
when compared with multiple chip solutions. The
SST31LF021/021E inherently use less energy during
Erase and Program than alternative flash technologies.
When programming a flash device, the total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter Erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative
flash technologies. The monolithic ComboMemory elimi-
nates redundant functions when using two separate mem-
ories of similar architecture; therefore, reducing the total
power consumption.
SRAM Read
The SRAM Read operation of the SST31LF021/021E are
controlled by OE# and BES#, both have to be low with
WE# high, for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. When BES# and
BEF# are high, both memory banks are deselected. OE#
is the output control and is used to gate data from the out-
put pins. The data bus is in high impedance state when
OE# is high. See Figure 2 for the Read cycle timing dia-
gram.
SRAM Write
The SRAM Write operation of the SST31LF021/021E are
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. BES# is used for SRAM bank
selection. During the Byte-Write operation, the addresses
and data are referenced to the rising edge of either BES#
or WE#, whichever occurs first. The Write time is measured
from the last falling edge to the first rising edge of BES# and
WE#. See Figure 3 for the Write cycle timing diagram.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
The SST31LF021/021E devices also improve flexibility by
using a single package and a common set of signals to
perform functions previously requiring two separate
devices. To meet high density, surface mount requirements,
the SST31LF021/021E devices are offered in 32-lead
TSOP packages. See Figure 1 for the pinouts.
Flash Operation
With BEF# active, the SST31LF021/021E operate as a
256K x8 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and internally
timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. Bus
contention is eliminated as the monolithic device will not
recognize both bank enables as being simultaneously
active. If both bank enables are asserted (i.e., BEF# and
BES# are both low), the BEF# will dominate while the
BES# is ignored and the appropriate operation will be exe-
cuted in the flash memory bank. SST does not recommend
that both bank enables be simultaneously asserted. All
other address, data, and control lines are shared; which
minimizes power consumption and area. The device goes
into standby when both bank enables are raised to VIHC.
Flash Read
The Read operation of the SST31LF021/021E devices are
controlled by BEF# and OE#, both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when OE# is high. See Figure 4
for the Read cycle timing diagram.
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
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SST [ SILICON STORAGE TECHNOLOGY, INC ]
