2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During flash Sector-Erase, A17-A12 address lines will select the sector.
A17-A0 to provide flash address
A16-A0 to provide SST31LF021/021E SRAM
addresses
DQ7-DQ0
Data Input/Output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
BEF#
OE#
WE#
VDD
SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low.
Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low.
Output Enable
Write Enable
Power Supply
Ground
To gate the data output buffers.
To control the Write operations.
3.0-3.6V Power Supply
VSS
T2.3 392
1. AMS = Most significant address
TABLE 3: OPERATION MODES SELECTION
Mode
BES#
BEF#
OE#
WE#
A9 DQ
Address
Flash
Read
X1
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
AIN DOUT
AIN DIN
AIN
Program
Erase
AIN
X
X
X
Sector address,
XXH for Bank-Erase
SRAM
Read
VIL
VIL
VIHC
X
VIH
VIH
VIHC
X
VIL
X
VIH
VIL
X
AIN DOUT
AIN DIN
AIN
AIN
X
Write
Standby
X
X
X
X
X
High Z
Flash Write Inhibit
VIL
X
X
High Z / DOUT
High Z / DOUT
High Z / DOUT
X
X
X
VIH
X
X
X
VIH
X
X
Product Identification
Hardware Mode
X
X
VIL
VIL
VIL
VIL
VIH
VIH
VH Manufacturer’s ID (BFH)
Device ID2
A17-A1=VIL, A0=VIL
A17-A1=VIL, A0=VIH
Software Mode
AIN ID Code
See Table 4
T3.4 392
1. X can be VIL or VIH, but no other value.
2. Device ID 18H for SST31LF021, 19H for SST31LF021E.
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
6
SST [ SILICON STORAGE TECHNOLOGY, INC ]
