2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
OE#
WE#
T
T
DS
CPH
T
AS
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
Note:
A
A
= Most significant address
MS
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A
16
17
18
MS
X can be V or V but no other value.
IL
IH,
1117 F05.4
FIGURE 7: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
MS-0
T
CE
CE#
T
T
OEH
OES
OE#
WE#
T
OE
DQ
7
DATA
DATA#
DATA#
DATA
Note:
A
MS
A
MS
= Most significant address
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A
16 17 18
1117 F06.3
FIGURE 8: Data# Polling Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71117-09-000
2/07
16