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SST39VF800-70-4C-EK 参数 Datasheet PDF下载

SST39VF800-70-4C-EK图片预览
型号: SST39VF800-70-4C-EK
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 512K ×16位)多用途闪存 [8 Megabit (512K x 16-Bit) Multi-Purpose Flash]
分类和应用: 闪存
文件页数/大小: 23 页 / 251 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
T
ABLE
8: DC O
PERATING
C
HARACTERISTICS
V
DD
= 2.7-3.6V
AND
V
DDQ
= V
DD OR
4.5V - 5.5V
Symbol Parameter
I
DD
Min
Limits
Max
20
25
10
10
1
1
0.8
Units
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
V
µA
Test Conditions
CE#=OE#=V
IL,
WE#=V
IH
, all I/Os open,
Address input = V
IL
/V
IH
, at f=1/T
RC
Min.
CE#=WE#=V
IL,
OE#=V
IH,
V
DD
=V
DD
Max.
CE#=V
IHC
, V
DD
= V
DD
Max.
CE#=V
IHC
, V
DD
= V
DD
Max.
V
IN
=GND to V
DD
, V
DD
= V
DD
Max.
V
OUT
=GND to V
DD
, V
DD
= V
DD
Max.
V
DD
= V
DD
Min.
V
DD
= V
DD
Max.
V
DD
= V
DD
Max.
V
DD
= V
DD
Max.
I
OL
= 100 µA, V
DD
= V
DD
Min.
I
OH
= -100 µA, V
DD
= V
DD
Min.
CE# = OE# =V
IL
, WE# = V
IH
CE# = OE# = V
IL
, WE# = V
IH
, A
9
= V
H
Max.
343 PGM T9.1
1
2
3
4
5
6
7
8
9
343 PGM T10.0
I
SB
I
ALP
I
LI
I
LO
V
IL
V
ILC
V
IH
V
IHC
V
OL
V
OH
V
H
I
H
Power Supply Current
Read
Program and Erase
Standby V
DD
Current
Auto Low Power Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
0.3
Input High Voltage
2.0
Input High Voltage (CMOS) V
DD
-0.3
Output Low Voltage
Output High Voltage
2.4
Supervoltage for A
9
pin
11.4
Supervoltage Current
for A
9
pin
0.4
12.6
200
T
ABLE
9: R
ECOMMENDED
S
YSTEM
P
OWER
-
UP
T
IMINGS
Symbol
Parameter
T
PU-READ(1)
T
PU-WRITE(1)
Power-up to Read Operation
Power-up to Program/Erase
Operation
Minimum
100
100
Units
µs
µs
T
ABLE
10: C
APACITANCE
(Ta = 25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
C
I/O(1)
C
IN(1)
Note:
(1) This
10
11
Maximum
12 pF
6 pF
343 PGM T11.1
I/O Pin Capacitance
Input Capacitance
V
I/O
= 0V
V
IN
= 0V
parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
12
13
T
ABLE
11: R
ELIABILITY
C
HARACTERISTICS
Symbol
Parameter
Minimum Specification
N
END(1)
T
DR(1)
V
ZAP_HBM(1)
V
ZAP_MM(1)
I
LTH(1)
Endurance
Data Retention
ESD Susceptibility
Human Body Model
ESD Susceptibility
Machine Model
Latch Up
10,000
100
1000
200
100 + I
DD
Units
Cycles
Years
Volts
Volts
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
JEDEC Standard A115
JEDEC Standard 78
343 PGM T12.1
14
15
16
Note:
(1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
© 1999 Silicon Storage Technology, Inc.
9
343-04 2/99