4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 21: R
ESET
T
IMING
P
ARAMETERS
(PP M
ODE
), V
DD
=3.0-3.6V
Symbol
T
PRST
T
RSTP
T
RSTF
T
RST1
T
RSTE
T
RSTC
Parameter
V
DD
stable to Reset Low
RST# Pulse Width
RST# Low to Output Float
RST# High to Row Address Setup
RST# Low to reset during Sector-/Block-Erase or Program
RST# Low to reset during Chip-Erase
1
10
50
Min
1
100
48
Max
Units
ms
ns
ns
µs
µs
µs
T21.0 562
1. There will be a reset latency of T
RSTE
or T
RSTC
if a reset procedure is performed during a programming or erase operational.
VDD
TPRST
Addresses
Row Address
R/C#
RST#
TRSTP
TRSTE
Sector-/Block-Erase
or Program operation
aborted
Chip-Erase
aborted
TRSTC
TRSTF
TRST
DQ7-0
562 ILL F18.0
FIGURE 18: R
ESET
T
IMING
D
IAGRAM
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
31
SST [ SILICON STORAGE TECHNOLOGY, INC ]
