4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
LAD[3:0]
Start
0000b
Memory
Read
Cycle
010Xb
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
A[15:12] A[11:8]
Load Address in 8 Clocks
A[7:4]
A[3:0]
TAR
1111b
Tri-State
Sync
0000b
1 Clock
Data
D[3:0]
D[7:4]
TAR
Start next
0000b
1 Clock
562 ILL F16.2
1 Clock 1 Clock
2 Clocks
Data out 2 Clocks
Note: See Tables 4 and 5 Register Addresses
FIGURE 17: GPI R
EGISTER
R
EADOUT
T
IMING
D
IAGRAM
(LPC M
ODE
)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
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