4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
LAD[3:0]
1st Start
0000b
Memory
Write
Cycle
011Xb
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
Data
1010b
1010b
TAR
1111b
Sync
TAR
1 Clock
Start next
Command
Tri-State 0000b
1 Clock
1 Clock 1 Clock
Load Address "YYYY 5555H" in 8 Clocks
Load Data "AAH" in 2 Clocks 2 Clocks
Write the 1st command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
2nd Start
0000b
Memory
Write
Cycle
011Xb
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
0010b
1010b
1010b
1010b
Data
0101b
0101b
TAR
1111b
Sync
TAR
1 Clock
Start next
Command
LAD[3:0]
Tri-State 0000b
1 Clock
1 Clock 1 Clock
Load Address "YYYY 2AAAH" in 8 Clocks
Load Data "55H" in 2 Clocks 2 Clocks
Write the 2nd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
3rd Start
Memory
Write
Cycle
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
Data
0000b
1000b
TAR
1111b
Tri-State
Sync
0000b
1 Clock
TAR
Start next
Command
1 Clock
LAD[3:0]
0000b 011Xb
1 Clock 1 Clock
Load Address "YYYY 5555H" in 8 Clocks
Load Data "80H" in 2 Clocks 2 Clocks
Write the 3rd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
4th Start
Memory
Write
Cycle
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
Data
1010b
1010b
TAR
1111b
Tri-State
Sync
0000b
1 Clock
TAR
Start next
Command
1 Clock
LAD[3:0]
0000b 011Xb
1 Clock 1 Clock
Load Address "YYYY 5555H" in 8 Clocks
Load Data "AAH" in 2 Clocks 2 Clocks
Write the 4th command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
5th
Memory
Write
Cycle
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
0010b
1010b
1010b
1010b
Data
0101b
0101b
TAR
1111b Tri-State
Sync
0000b
1 Clock
TAR
Start next
Command
1 Clock
LAD[3:0]
0000b 011Xb
1 Clock 1 Clock
Load Address "YYYY 2AAA" in 8 ClocksH
Load Data "55H" in 2 Clocks 2 Clocks
Write the 5th command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
Internal
erase start
LFRAME#
6th Start
Memory
Write
Cycle
011Xb
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
SAX
XXXXb XXXXb
XXXXb
Data
0000b
0011b
TAR
1111b
Tri-State
Sync
0000b
1 Clock
TAR
Internal
erase start
LAD[3:0]
0000b
1 Clock 1 Clock
Load Sector Address in 8 Clocks
Load Data “30” in 2 Clocks
2 Clocks
Write the 6th command (target sector to be erased) to the device in LPC mode.
SAX = Sector Address
Note: YYYY must be within memory address range specified in Figures 4 and 5.
562 ILL F14.1
FIGURE 15: S
ECTOR
-E
RASE
T
IMING
D
IAGRAM
(LPC M
ODE
)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
27
SST [ SILICON STORAGE TECHNOLOGY, INC ]
