4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 1: P
IN
D
ESCRIPTION
Interface
Type
1
PP LPC Functions
I
X
Inputs for low-order addresses during Read and Write operations. Addresses are
internally latched during a Write cycle. For the programming interface, these
addresses are latched by R/C# and share the same pins as the high-order
address inputs.
DQ
7
-DQ
0
Data
I/O
X
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# is high.
OE#
Output Enable
I
X
To gate the data output buffers.
WE#
Write Enable
I
X
To control the Write operations.
MODE
Interface
I
X
X
This pin determines which interface is operational. When held high, programmer
Mode Select
mode is enabled and when held low, LPC mode is enabled. This pin must be
setup at power-up or before return from reset and not change during device oper-
ation. This pin must be held high (V
IH
) for PP mode and low (V
IL
) for LPC mode.
INIT#
Initialize
I
X
This is the second reset pin for in-system use. This pin is internally combined
with the RST# pin; If this pin or RST# pin is driven low, identical operation is
exhibited.
ID[3:0]
Identification
I
X
These four pins are part of the mechanism that allows multiple parts to be attached
or
Inputs
to the same bus. These pins are internally pulled-down with a resistor between 20-
ID[3:1]
100 KΩ
GPI[4:0]
General
I
X
These individual inputs can be used for additional board flexibility. The state of
Purpose Inputs
these pins can be read through LPC registers. These inputs should be at their
desired state before the start of the PCI clock cycle during which the read is
attempted, and should remain in place until the end of the Read cycle. Unused
GPI pins must not be floated.
TBL#
Top Block Lock
I
X
When low, prevents programming to the boot block sectors at top of memory.
When TBL# is high it disables hardware write protection for the top block sectors.
This pin cannot be left unconnected.
LAD[3:0] Address and
I/O
X
To provide LPC control signals, as well as addresses and Command
Data
Inputs/Outputs data.
LCLK
Clock
I
X
To provide a clock input to the control unit
LFRAME# Frame
I
X
To indicate start of a data transfer operation; also used to abort an LPC cycle
in progress.
RST#
Reset
I
X
X
To reset the operation of the device
WP#
Write Protect
I
X
When low, prevents programming to all but the highest addressable blocks.
When WP# is high it disables hardware write protection for these blocks.
This pin cannot be left unconnected.
I
X
Select for the Programming interface, this pin determines whether the address
R/C#
Row/Column
Select
pins are pointing to the row addresses, or to the column addresses.
RES
Reserved
X
These pins must be left unconnected.
Power Supply
PWR X
X
To provide power supply (3.0-3.6V)
V
DD
V
SS
Ground
PWR X
X
Circuit ground (0V reference)
CE#
Chip Enable
I
X
This signal must be asserted to select the device. When CE# is low, the device
is enabled. CE# must remain low during internal Write (Program or Erase)
operations. When CE# is high, the device is placed in low power Standby mode.
NC
No Connection
I
X
X
Unconnected pins.
Symbol
A
10
-A
0
Pin Name
Address
T1.4 562
1. I=Input, O=Output
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
8
SST [ SILICON STORAGE TECHNOLOGY, INC ]
