欢迎访问ic37.com |
会员登录 免费注册
发布采购

SST49LF040-33-4C-WH 参数 Datasheet PDF下载

SST49LF040-33-4C-WH图片预览
型号: SST49LF040-33-4C-WH
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位闪存LPC [4 Mbit LPC Flash]
分类和应用: 闪存PC
文件页数/大小: 48 页 / 711 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
 浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第8页浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第9页浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第10页浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第11页浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第13页浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第14页浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第15页浏览型号SST49LF040-33-4C-WH的Datasheet PDF文件第16页  
4 Mbit LPC Flash
SST49LF040
Advance Information
Registers
00FF FFFFH
Device #14
Device #15
Device #2
8 MByte
Register Access
There are two registers available on the SST49LF040, the
General Purpose Inputs Registers (GPI_REG) and the
JEDEC ID Registers. Since multiple LPC memory devices
may be used to increase memory densities, these registers
appear at its respective address location in the 4 GByte
system memory map. Unused register locations will read
as 00H. Any attempt to read registers during internal Write
operation will respond as “Write Operation Status Detec-
tion” (Data# Polling or Toggle Bit). Tables 4 and 5 list
GPI_REG and JEDEC ID address locations for
SST49LF040 with its respective device strapping.
TABLE 3: G
ENERAL
P
URPOSE
I
NPUTS
R
EGISTER
Pin #
Bit
7:5
4
Function
Reserved
GPI[4]
Reads status of general
purpose input pin
GPI[3]
Reads status of general
purpose input pin
GPI[2]
Reads status of general
purpose input pin
GPI[1]
Reads status of general
purpose input pin
GPI[0]
Reads status of general
purpose input pin
32-PLCC
-
30
32-TSOP
-
6
Device #3
Device #0
Device #1
(Boot Block)
Device #14
(Boot Block)
Device #15
0080 0000H
007F FFFFH
3
3
11
2
4
12
1
(Boot Block)
Device #2
(Boot Block)
Device #3
(Boot Block)
Boot Device #0
(Boot Block)
Device #1
0000 0000H
562 ILL F02.3
5
13
0
8 MByte
Memory Access
6
14
T3.1 562
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes
the state of GPI[4:0] pins at power-up on the SST49LF040.
It is recommended that the GPI[4:0] pins be in the desired
state before LFRAME# is brought low for the beginning of
the next bus cycle, and remain in that state until the end of
the cycle. There is no default value since this is a pass-
through register. See Table 3, General Purpose Inputs
Register, for the GPI_REG bits and functions and Tables 4
and 5 for memory address location for its respective device
strapping.
FIGURE 5: B
OOT
C
ONFIGURATION FROM THE
B
OTTOM OF THE
4 GB
YTE
S
YSTEM
M
EMORY
M
AP
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
12