4 Mbit LPC Flash
SST49LF040
Advance Information
With hardware strapping, ID bits in the address field is
included in every LPC address memory cycle. The address
bits [A22: A19] are used to select the device with proper
IDs. The ID strapping bits in the address field will be
decoded depending on where the device is mapped on the
4 GByte system memory map. See Table 2 for ID address
bits decoding. The device will compare these bits with
ID[3:0]’s strapping values. If there is a mismatch, the device
will ignore the remainder of the cycle.
TABLE 2: ID S
TRAPPING
V
ALUES
Hardware
Strapping
Device #
0 (Boot device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FOR
(Boot Block)
Boot Device #0
(Boot Block)
Device #1
(Boot Block)
FFFF FFFFH
SST49LF040
Device #2
(Boot Block)
Device #3
8 MByte
Memory Access
Address Bits [A
22
-A
19
]
Decoding
1
4 GByte System Memory
Top
1111b
1110b
1101b
1100b
1011b
1010b
1001b
1000b
0111b
0110b
0101b
0100b
0011b
0010b
0001b
0000b
Bottom
0001b
0000b
0011b
0010b
0101b
0100b
0111b
0110b
1001b
1000b
1011b
1010b
1101b
1100b
1111b
1110b
T2.3 562
(Boot Block)
Device #14
(Boot Block)
Device #15
FF80 0000H
FF7F FFFFH
Device #0
Device #1
Device #2
8 MByte
Register Access
1. Address bits A
22
-A
19
decoding for multiple device selection
depends on whether the device is mapped from the top of the
4GB system memory map or from the bottom of the 4GB
system memory map.
Device #3
Device #14
Device #15
FF00 0000H
562 ILL F01.1
FIGURE 4: B
OOT
C
ONFIGURATION FROM THE
T
OP
OF THE
4 GB
YTE
S
YSTEM
M
EMORY
M
AP
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
11
SST [ SILICON STORAGE TECHNOLOGY, INC ]
