STM8S105xx
Memory and register map
Address
Block
Register label Register name
Reset
status
0x00 500A Port C
0x00 500B
PC_ODR
Port C data output latch register
Port C input pin value register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
0x00 500C
Port C data direction register
Port C control register 1
0x00 500D
0x00 500E
Port C control register 2
0x00 500F Port D
0x00 5010
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00 5011
0x00 5012
0x00 5013
Port D control register 2
0x00 5014 Port E
0x00 5015
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
0x00 5016
0x00 5017
0x00 5018
Port E control register 2
0x00 5019 Port F
0x00 501A
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00 501B
PF_DDR
PF_CR1
0x00 501C
DocID14771 Rev 9
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STMICROELECTRONICS [ ST ]
