uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Figure 64. Peripheral I/O Mode
RD
PSEL0
PSEL
PSEL1
D0 - D7
DATA BUS
VM REGISTER BIT 7
PA0 - PA7
WR
AI02886
Table 92. Port Operating Modes
Port Mode
MCU I/O
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Address Out
Peripheral I/O
JTAG ISP
Yes
Yes
No
No
Yes
Yes (A7 – 0)
Yes
No
Port A
(1)
Yes
Yes
Yes
No
Yes
Yes (A7 – 0)
No
No
Port B
Yes
No
Yes
(2)
No
Yes
No
No
Yes
(3)
Port C
Yes
No
No
Yes
Yes
No
No
No
Port D
Note: 1. Port A is not available in the 52-pin package.
2. On pins PC2, PC3, PC4, and PC7 only.
3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
Table 93. Port Operating Mode Settings
Mode
MCU I/O
PLD I/O
Address Out
(Port A,B)
Peripheral I/O
(Port A)
Defined in PSDsoft
Declare pins only
Logic equations
Declare pins only
Logic equations
(PSEL0 & 1)
0
N/A
1
N/A
Control Register
Setting
(1)
Direction Register
Setting
(1)
1 = output,
0 = input (Note 2)
(Note 2)
1 (Note 2)
N/A
VM Register Setting
(1)
N/A
N/A
N/A
PIO Bit = 1
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
Table 94. I/O Port Latched Address Output Assignments
Port A (PA3-PA0)
Address a3-a0
Port A (PA7-PA4)
Address a7-a4
Port B (PB3-PB0)
Address a3-a0
Port B (PB7-PB4)
Address a7-a4
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