uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure
The two ports can be
configured to perform one or more of the following
functions:
– MCU I/O Mode
– CPLD Output – Macrocells McellAB7-
McellAB0 can be connected to Port A or Port
B. McellBC7-McellBC0 can be connected to
Port B or Port C.
Figure 65. Port A and Port B Structure
–
–
–
–
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched
address output as per
Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
Peripheral Mode – Port A only (80-pin
package)
DATA OUT
REG.
D
WR
ADDRESS
ALE
D
G
Q
Q
DATA OUT
ADDRESS
A[ 7:0]
PORT
A OR B PIN
OUTPUT
MUX
MACROCELL OUTPUTS
READ MUX
MCU DATA BUS
P
D
B
CONTROL REG.
D
WR
DIR REG.
D
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
Q
Q
ENABLE OUT
DATA IN
OUTPUT
SELECT
CPLD-INPUT
AI06605
124/170
STMICROELECTRONICS [ STMICROELECTRONICS ]
