uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD Module requires a Reset
(RESET) pulse of duration t
NLNH-PO
after V
CC
is
steady. During this period, the device loads inter-
nal configurations, clears some of the registers
and sets the Flash memory into operating mode.
After the rising edge of Reset (RESET), the PSD
Module remains in the Reset Mode for an addition-
al period, t
OPR
, before the first memory access is
allowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, WRITE
Strobe (WR, CNTL0) High, during Power-on
RESET for maximum security of the data contents
and to remove the possibility of a byte being writ-
ten on the first edge of WRITE Strobe (WR). Any
Flash memory WRITE cycle initiation is prevented
automatically when V
CC
is below V
LKO
.
Warm RESET
Once the device is up and running, the PSD Mod-
ule can be reset with a pulse of a much shorter du-
ration, t
NLNH
. The same t
OPR
period is needed
Figure 71. Reset (RESET) Timing
before the device is operational after a Warm
RESET. Figure
shows the timing of the Power-
up and Warm RESET.
I/O Pin, Register and PLD Status at RESET
Table
shows the I/O pin, register and PLD sta-
tus during Power-on RESET, Warm RESET, and
Power-down Mode. PLD outputs are always valid
during Warm RESET, and they are valid in Power-
on RESET once the internal Configuration bits are
loaded. This loading is completed typically long
before the V
CC
ramps up to operating level. Once
the PLD is active, the state of the outputs are de-
termined by the PLD equations.
Reset of Flash Memory Erase and Program
Cycles
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the READ Mode within a period of t
NLNH-A
.
V
CC
V
CC
(min)
tNLNH
tNLNH-A
Warm Reset
tNLNH-PO
Power-On Reset
tOPR
tOPR
RESET
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