uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the uPSD323X Devices:
➜
DC Electrical Specification
➜
AC Timing Specification
■
PLD Timing
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Macrocell Timing
■
MCU Module Timing
– READ Timing
– WRITE Timing
– Power-down and RESET Timing
The following are issues concerning the parame-
ters presented:
– In the DC specification the supply current is
given for different modes of operation.
– The AC power component gives the PLD,
Flash memory, and SRAM mA/MHz
specification. Figures
and
show the PLD
mA/MHz as a function of the number of
Product Terms (PT) used.
– In the PLD timing parameters, add the
required delay when Turbo Bit is '0.'
Figure 72. PLD I
CC
/Frequency Consumption (5V range)
110
100
90
80
I
CC
– (mA)
70
FF
O
V
CC
= 5V
)
00%
N (1
O
BO
TUR
60
TU
RB
50
40
30
20
10
0
0
5
ON
BO
TUR
(25%
)
O
O
RB
TU
F
OF
PT 100%
PT 25%
10
15
20
25
AI02894
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Figure 73. PLD I
CC
/Frequency Consumption (3V range)
60
V
CC
= 3V
50
I
CC
– (mA)
40
ON (
RBO
TU
100%
)
O
FF
30
20
10
TU
RB
O
(25
O ON
TU R B
%)
O
RB
TU
0
0
5
F
OF
PT 100%
PT 25%
10
15
20
25
AI03100
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
135/170
STMICROELECTRONICS [ STMICROELECTRONICS ]
