uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
REVISION HISTORY
Table 150. Document Revision History
Date
November 2002
Version
1.0
First Issue
Updates: product information (Figure
Table
1, 2);
port information (Figure
Table
interface information (Figure
Table
remove programming guide; PSD
Module information (Figure
Table
PLD information (Figure
Table
electrical characteristics (Table
Updated references for Product Catalog
Reformatted; corrected mechanical dimensions (Table
Reformatted; added EMC characteristics (Table
Updates according to data brief change request (Figure
Table
1, 2, 116)
Revision Details
27-Feb-03
1.1
02-Sep-03
04-Feb-04
05-Jul-04
04-Nov-04
1.2
2.0
3.0
4.0
Table 151. Device Functional Change History
Functional Change
PWM Block
After Date Code 0242
An 8-bit, Programmable PWM 4 channel
and the associated registers are added.
When DDC is disabled, the data space
FF00h-FFFFh assigned to DDC SRAM is
available for external data mapping. The
SWENB Bit definition in the DDCON
Register is modified.
1.
USB Reset Function
2.
3.
Option to block USB generated reset
from resetting the MCU/PSD modules.
Allow USB Reset Flag (RSTF) to
interrupt MCU.
Add RSTE and RSTFIE Bits to the
UIEN Interrupt Enable Register.
Date Code 0242 and before
Only PWM0-PWM3 channels are
available.
DDC SRAM Mapping
Data space FF00h-FFFFh is dedicated to
DDC SRAM.
USB-generated reset always resets both,
the USB and the MCU/PSD modules.
Note: Date Code is the 6th to the 9th digit of the Trace Code on top of the device.
169/170
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