SMM150
Preliminary Information
INTERNAL BLOCK DIAGRAM
READY
FAULT#
VDD
VDD_CAP
GND
VREF
VREF =
1.25V or 0.5V
COMP1
OV/UV
Output
Control
Glitch
Filter
OV/UV
V
REF
COMP2
50kΩ
Up/Dn
MUP
MDN
Margin
Target
Digital
Comparator
Halt
Control
Logic
8-bit DAC
SW1
TRIM
50kΩ
Clock
A0
A1
A2
SCL
SDA
WP
I
2
C
Interface
10Bit
ADC
MUX
SW2
VM
EE
Configuration
Registers
& Memory
CAPM
Figure 2 – SMM150 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pad QFN
Top View
20 Ball
Ultra
CSP
TM
Bottom View
SDA
NC
NC
MDN
MUP
VDD_CAP
NC
Pin 1
SCL
MDN VDD_CAP VDD
Pin 1
28 27 26 25 24 23 22
A1
21
20
A2
SDA
A3
TRIM
A4
COMP1
SCL
A2
NC
A1
READY
A0
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14
GND
SMM150
or
NC
19
18
17
16
15
VDD
TRIM
COMP1
NC
NC
NC
NC
A2
B1
A1
B2
READY
B3
MUP
B4
NC
C1
A0
C2
WP
C3
FAULT#
C4
NC
D1
GND
D2
E2
D3
E3
D4
VM
CAP_M COMP2
WP
NC
CAP_M
FAULT#
COMP2
NC
VM
E1
E4
Summit Microelectronics, Inc
2075 2.6 05/13/05
3
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
