SMM150
Preliminary Information
I
2
C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 3 Timing Diagram.
Symbol
f
SCL
t
LOW
t
HIGH
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
AA
t
DH
t
R
t
F
t
SU:DAT
t
HD:DAT
TI
t
WR
Description
SCL Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock Edge to Data Valid
Data Output Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
Write Cycle Time
Conditions
Min
0
4.7
4.0
Typ
Max
100
Units
KHz
µs
µs
µs
µs
µs
µs
Before New Transmission
-
Note
1/
4.7
4.7
4.0
4.7
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA
change
Note
1/
Note
1/
0.2
0.2
3.5
µs
µs
1000
300
250
0
ns
ns
ns
ns
Noise suppression
100
5
ns
ms
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
t
R
SCL
t
SU:SDA
SDA
(IN)
t
F
t
HD:SDA
t
HIGH
t
W R (For W rite O peration Only)
t
LOW
t
SU:DAT
t
SU:STO
t
BUF
t
HD:DAT
t
AA
SDA
(OUT)
t
DH
Figure 3. Basic I
2
C Serial Interface Timing
Summit Microelectronics, Inc
2075 2.6 05/13/05
7
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
