SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
SPFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
SPFS1
0
0
1
1
SPFS0
0
1
0
1
Divider
2
4
8
16
SPWM clock, Fosc=20MHz
10MHz
5MHz
2.5MHz
1.25MHz
SPWM clock, Fosc=24MHz
12MHz
6MHz
3MHz
1.5MHz
SPWM Registers - SPWM Data Register (SPWMD0, 0A4H)
bit-7
SPWMD04
Read/Write:
Reset value:
R/W
0
SPWMD03
R/W
0
SPWMD02
R/W
0
SPWMD01
R/W
0
SPWMD00
R/W
0
BRM02
R/W
0
BRM01
R/W
0
bit-0
BRM00
R/W
0
SPWMD0[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[2:0]
000
001
010
011
100
101
110
111
Number of SPWM cycles inserted in an 8-cycle frame
0
1
2
3
4
5
6
7
Example of SPWM timing diagram:
MOV SPWMD0 , #83H
MOV P1CON , #04H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3
; Enable P1.2 as SPWM output pin
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/26
Preliminary
Ver 1.0
SM79108 01/03
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
