SyncMOS Technologies Inc.
January 2003
3. Port 4 for PLCC or QFP package:
Preliminary
SM79108
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, 0D8H)
bit-7
Unused
Read / Write:
Reset value:
-
*
Unused
-
*
Unused
-
*
Unused
-
*
P4.3
R/W
1
P4.2
R/W
1
P4.1
R/W
1
bit-0
P4.0
R/W
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
4. SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock
speed. The SPFS[1:0] settings of SPWMC (0A3H) register are divided of Fosc to be SPWM clock, Fosc/
2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/
2^(SPFS[1:0]+1)]/32.
4.1 SPWM Registers - P1CON, SPWMC0, SPWMD0
SPWM Registers - Port1 Configuration Register (P1CON, 9BH)
bit-7
Unused
Read / Write:
Reset value:
-
*
Unused
-
*
PWME0
R/W
0
Unused
-
*
Unused
-
*
SPWME0
R/W
0
Unused
-
*
bit-0
Unused
-
*
SPWME0 : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset
to zero, the corresponding SPWM pin is active as I/O pin. Four bits are cleared upon reset.
PWME0 : When the bit set to one, the corresponding PWM pin is active as PWM function. When the bit reset
to zero, the corresponding PWM pin is active as I/O pin. Four bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, 0A3H)
bit-7
Unused
Read / Write:
Reset value:
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
SPFS1
R/W
0
bit-0
SPFS0
R/W
0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/26
Preliminary
Ver 1.0
SM79108 01/03
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
