SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
Watch Dog Timer Registers - WDT Control Register (WDTC, 9FH)
bit-7
WDTE
Read / Write:
Reset value:
R/W
0
R
-
0
CLEAR
R/W
0
Unused
-
*
Unused
-
*
PS2
R/W
0
PS1
R/W
0
bit-0
PS0
R/W
0
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
000
001
010
011
100
101
110
111
Overflow Period (ms)
2.048
4.096
8.192
16.384
32.768
65.536
131.072
262.144
System Control Register (SCONF, 0BFH)
bit-7
WDR
Read / Write:
Reset value:
R/W
0
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Reserved
-
*
Unused
-
*
bit-0
ALEI
R/W
0
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ALEI : ALE output inhibit bit, to reduce EMI
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever unpredicted reset happened.
2. Reduce EMI Function
The SM79108 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/26
Preliminary
Ver 1.0
SM79108 01/03
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
