C2510Fx / CC2511Fx
13.14 USART
USART0
and
USART1
are
serial
communications interfaces that can be
operated separately in either asynchronous
UART mode or in synchronous SPI mode. The
two USARTs are identical in functionality but
are assigned to separate I/O pins. Refer to
Section 13.4 on Page 88 for I/O configuration.
13.14.1
UART Mode
When
the
transmission
ends,
the
bit is set to 1. The USARTx
TX
complete
CPU
interrupt
flag
register is ready to accept new
transmit data, and an interrupt request is
generated if
This happens
immediately after the transmission has been
started, hence a new data byte value can be
loaded into the data buffer while the byte is
being transmitted.
13.14.1.2 UART Receive
Data reception on the UART is initiated when a
1 is written to the
bit. The UART
will then search for a valid start bit on the
RXDx input pin and set the
bit
high. When a valid start bit has been detected
the received byte is shifted into the receive
register. The
bit and the
CPU interrupt flag,
is set to 1
when the operation has completed and an
interrupt
request
is
generated
if
At
the
same
time
will go low.
The received data byte is available through the
register. When
is read,
is cleared by hardware.
13.14.1.3 UART Hardware Flow Control
Hardware flow control is enabled when the
bit is set to 1. The RTS output
will then be driven low when the receive
register is empty and reception is enabled.
Transmission of a byte will not occur before
the CTS input go low.
13.14.1.4 UART Character Format
If the
and
bits in register
UxUCR
are set high, parity generation and detection is
enabled. The parity is computed and
transmitted as the ninth bit, and during
reception, the parity is computed and
compared to the received ninth bit. If there is a
parity error, the
bit is set high.
This bit is cleared when
is read.
The number of stop bits to be transmitted is set
to one or two bits determined by the register bit
The receiver will always check for
one stop bit. If the first stop bit received during
reception is not at the expected stop bit level, a
framing error is signaled by setting register bit
high.
is cleared when
For asynchronous serial interfaces, the UART
mode is provided. In UART mode the interface
uses a two-wire or four-wire interface
consisting of the pins RXD and TXD, and
optionally RTS and CTS. The UART mode
includes the following features:
•
8 or 9 data bits
•
Odd, even, or no parity
•
Configurable start and stop bit level
•
Configurable LSB or MSB first transfer
•
Independent
interrupts
receive
and
transmit
•
Independent receive and transmit DMA
triggers
•
Parity and framing error status
The UART mode provides full duplex
asynchronous
transfers
and
the
synchronization of bits in the receiver does not
interfere with the transmit function. A UART
byte transfer consists of a start bit, eight data
bits, an optional ninth data or parity bit, and
one or two stop bits. Note that the data
transferred is referred to as a byte, although
the data can actually consist of eight or nine
bits.
The UART operation is controlled by the
USART x Control and Status registers,
and the USART x UART Control register,
where x is the USART number, 0 or 1.
The UART mode is
is set to 1.
13.14.1.1 UART Transmit
A UART transmission is initiated when the
USART
Receive/Transmit
Data
Buffer,
register is written. The byte is
transmitted on the TXDx output pin. The
register is double-buffered.
The
bit goes high when the
byte transmission starts and low when it ends.
selected
when
SWRS055D
Page 152 of 243
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