SNLS420B – JULY 2012 – REVISED APRIL 2013
DS90UB914Q Deserializer Pin Descriptions (continued)
Pin Name
Pin No.
I/O, Type
Description
Device mode select pin
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. The MODE pin on the Deserializer
can be used to configure the Serializer and Deserializer to work in different input
PCLK range. See details in
12– bit low frequency mode – (10- 50 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 12 bits DATA+2 SYNC.
Input PCLK range is from 10MHz to 50MHz.
Input, LVCMOS
12– bit high frequency mode – (15-75 MHz operation):
In this mode, the Serializer
w/ pull up
and Deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK range is from
15MHz to 75MHz.
10–bit mode– (20–100 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 10 bits DATA + 2
SYNC. Input PCLK frequency can range from20 MHz to 100MHz.
Please refer to
in the
section on how to configure the
MODE pin on the Deserializer.
Input, analog
The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C device
address. Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to set programmable Device ID address
MODE
37
IDx[0:1]
35,34
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
Input, LVCMOS
PDB = L, Deserializer is in Sleep (power down mode). When the Deserializer is in
w/ pull down
Sleep, programmed control register data are NOT retained and reset to default
values.
Output,
LVCMOS
Input
LVCMOS w/
pulldown
Output,
LVCOMS
Input
LVCMOS w/
pulldown
Input
LVCMOS w/
pulldown
Input
LVCMOS w/
pulldown
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
BIST Enable pin
BISTEN=H,
BIST Mode Enabled
BISTEN=L,
BIST Mode is disabled
PASS Output Pin for BIST mode.
PASS = H,
ERROR FREE Transmission
PASS = L,
one or more errors were detected in the received payload.
See
section for more information. Leave Open if unused. Route to
test point (pad) recommended.
Output Enable Input
Refer to
Output Sleep State Select Pin
Refer to
MUX Select line
SEL = L,
RIN0+/- input. This selects input A as the active channel on the Deserializer.
SEL = H,
RIN1+/- input. This selects input B as the active channel on the
Deserializer.
Non-Inverting Differential input, bidirectional control channel. The IO must be AC
coupled with a 100 nF capacitor
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 100 nF capacitor
Non-Inverting Differential input, bidirectional control channel. The IO must be AC
coupled with a 100 nF capacitor
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 100 nF capacitor
Reserved.
This pin must always be tied low
Route to test point or leave open if unused
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from V
DDIO
. V
DDIO
can be connected to a 1.8V ±5% or 3.3V ±10%
Copyright © 2012–2013, Texas Instruments Incorporated
PDB
30
LOCK
48
BISTEN
6
PASS
47
OEN
5
OSS_SEL
4
SEL
46
FPD–Link III INTERFACE
RIN0+
RIN0-
RIN1+
RIN1-
RES
CMLOUTP/N
41
42
32
33
43,44
38,39
Input/Output,
CML
Input/Output,
CML
Input/Output,
CML
Input/Output,
CML
—
POWER AND GROUND
VDDIO1/2/3
6
29, 20, 7
Power, Digital
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