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DS90UB914Q 参数 Datasheet PDF下载

DS90UB914Q图片预览
型号: DS90UB914Q
PDF下载: 下载PDF文件 查看货源
内容描述: DS90UB913Q / DS90UB914Q 10-100MHz 10 / 12位DC平衡的FPD -Link的III串行器和解串与双向控制通道 [DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel]
分类和应用: 光电二极管
文件页数/大小: 63 页 / 1331 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Electrical Characteristics
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
V
OL
I
OS
Parameter
Low Level Output
Voltage
Output Short Circuit
Current
Conditions
V
DDIO
= 1.71V to 1.89V Deserializer
I
OL
= +4 mA
LVCMOS Outputs
V
OUT
= 0V
Serializer
GPO Outputs
Deserializer
LVCMOS Outputs
I
OZ
TRI-STATE® Output
Current
High Level Input
Voltage
Low Level Input
Voltage
Input Current
High Level Output
Voltage
Low Level Output
Voltage
Output Short Circuit
Current
PDB = 0V,
V
OUT
= 0V or V
DD
V
IN
= 2.52V to 3.08V
V
IN
= 2.52V to 3.08V
V
IN
= 0V or 3.08V
V
IN
= 2.52V to 3.08V
V
DDIO
= 2.52V to 3.08V
I
OH
=
−4
mA
V
DDIO
=2.52V to 3.08V
I
OL
= +4 mA
V
OUT
= 0V
Deserializer
LVCMOS Outputs
Serializer
GPO Outputs
Deserializer
LVCMOS Outputs
I
OZ
TRI-STATE® Output
Current
Output Differential
Voltage
Output Differential
Voltage Unbalance
Output Differential
Offset Voltage
Offset Voltage
Unbalance
Output Short Circuit
Current
PDB = 0V,
V
OUT
= 0V or V
DD
LVCMOS Outputs
-20
LVCMOS Outputs
-20
Min
GND
-11
mA
-17
+20
µA
Typ
Max
0.45
Units
V
LVCMOS DC SPECIFICATIONS 2.8V I/O (SER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
V
IH
V
IL
I
IN
V
OH
V
OL
I
OS
0.7 V
IN
GND
-20
V
DDIO
- 0.4
GND
-11
mA
-20
+20
µA
±1
V
IN
V
0.3 V
IN
+20
V
DDIO
0.4
µA
V
V
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|V
OD
|
ΔV
OD
V
OS
ΔV
OS
I
OS
R
T
R
L
= 100Ω (Figure
8)
R
L
= 100Ω
R
L
= 100Ω (Figure
8)
R
L
= 100Ω
DOUT+/- = 0V
80
268
340
1
V
DD
-
V
OD/2
1
-26
100
120
50
412
50
mV
mV
V
mV
mA
Differential Internal
Differential across DOUT+ and DOUT-
Termination Resistance
Input Current
V
IN
= V
DD
or 0V,
V
DD
= 1.89V
CML RECEIVER DC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )
I
IN
R
T
-20
80
1
100
+20
120
µA
Differential Internal
Differential across RIN+ and RIN-
Termination Resistance
Minimum allowable
swing for 1010
pattern
(4)
Differntial Output Eye
Opening
Differential Output Eye
Height
Line Rate = 1.4Gbps (Figure
CML RECEIVER AC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )
|V
swing
|
135
mV
CMLMONITOR OUTPUT DRIVER SPECIFICATIONS(CMLOUTP, CMLOUTN)
E
w
E
H
R
L
= 100Ω
Jitter Frequency>f/40 (Figure
0.45
200
UI
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
(4)
Specification is ensured by characterization and is not tested in production.
9
Copyright © 2012–2013, Texas Instruments Incorporated
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