15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
PIN DESCRIPTIONS
40-Pin DIP
Pin No.
1
2
3
4
5
6
Symbol
CS
CE
WR
RD
CONT/DEMAND
OVR/POL
Description
Chip select, active HIGH. Logically ANDed with CE to enable read and write inputs. (See
note 4.)
Chip enable, active LOW. (See note 5.)
Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and in demand
mode (CONT/DEMAND = LOW), a logic LOW on WR starts a conversion. (See note 4.)
Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD enables the
3-state data outputs. (See note 5.)
Conversion control input. When CONT/DEMAND = LOW, conversions are initiated by the WR
input. When CONT/DEMAND = HIGH, conversions are performed continuously. (See note 4.)
Overrange/polarity data-select input. When making conversions in the demand mode (CONT/
DEMAND = LOW), OVR/POL controls the data output on DB7 when the high-order byte is
active. (See note 5.)
Low/high byte-select input. When CONT/DEMAND = LOW, this input controls whether low-
byte or high-byte data is enabled on DB0 through DB7. (See note 5.)
Most significant data bit output. When reading the A/D conversion result, the polarity,
overrange, and DB7 data are output on this pin. (See text.)
Data outputs DB6–DB0. 3-state, bus compatible.
A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the deintegrate
phase and goes LOW when conversion is complete. The falling edge of BUSY can be used to
generate a
µP
interrupt.
Crystal oscillator connection or external oscillator input.
Crystal oscillator connection.
For factory testing purposes only. Do not make external connection to this pin.
Digital ground connection.
Connection for comparator auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Negative power supply connection, typically – 5V.
Output of the integrator amplifier. Connect to C
INT
.
Input to the integrator amplifier. Connect to summing node of R
INT
and C
INT
.
Output of the input buffer. Connect to R
INT
.
Connection for buffer auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Connection to buffer auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Connection for integrator auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Connection for integrator auto-zero capacitor. Bypass to V
SS
with 0.1
µF.
Analog common.
Negative differential analog input.
Analog common.
Positive input for reference voltage V
REF2
. (V
REF2
= V
REF1
/64)
Positive connection for V
REF2
reference capacitor.
Negative connection for V
REF2
reference capacitor.
Negative input for reference voltages.
Negative connection for V
REF1
reference capacitor.
Positive connection for V
REF1
reference capacitor.
Positive input for V
REF1
.
Positive power supply connection, typically +5V.
7
8
9 – 15
16
L/H
DB7
DB6–DB0
BUSY
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
30
33
34
35
36
37
38
39
40
OSC
1
OSC
2
TEST
DGND
COMP
V
SS
INT
OUT
INT
IN
BUFFER
C
BUFB
C
BUFA
C
INTA
C
INTB
COMMON
IN
–
COMMON
REF
2+
C
REF2+
C
REF2–
REF
–
C
REF1–
C
REF1+
REF
1+
V
DD
NOTES:
4. This pin incorporates a pull-down resistor to DGND.
5. This pin incorporates a pull-up resistor to V
DD
.
3-80
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
