15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
THEORY OF OPERATION
The TC850 is a multiple-slope, integrating analog-to-
digital converter (ADC). The multiple-slope conversion pro-
cess, combined with chopper-stabilized amplifiers, results
in a significant increase in ADC speed, while maintaining
very high resolution and accuracy.
1
Multiple-Slope Conversion Principles
One limitation of the dual-slope measurement tech-
nique is conversion speed. In a typical dual-slope method,
the auto-zero and integrate times are each one-half of the
deintegrate time. For a 15-bit conversion, 2
14
+ 2
14
+ 2
15
(65,536) clock pulses are required for auto-zero, integrate,
and deintegrate phases, respectively. The large number of
clock cycles effectively limits the conversion rate to about
2.5 conversions per second, when a typical analog CMOS
fabrication process is used.
The TC850 uses a multiple-slope conversion technique
to increase conversion speed (Figure 2B). This technique
makes use of a two-slope deintegration phase and permits
15-bit resolution up to 40 conversions per second.
During the TC850's deintegration phase, the integration
capacitor is rapidly discharged to yield a resolution of 9 bits.
At this point, some charge will remain on the capacitor. This
remaining charge is then slowly deintegrated, producing an
+5V
–5V
2
3
4
5
6
7
Dual-Slope Conversion Principles
The conventional dual-slope converter measurement
cycle (shown in Figure 2A) has two distinct phases:
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An oppo-
site polarity constant reference voltage is then integrated
until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, complete conversion
requires the integrator output to "ramp-up" and "ramp-
down." Most dual-slope converters add a third phase, auto-
zero. During auto-zero, offset voltages of the input buffer,
integrator, and comparator are nulled, thereby eliminating
the need for zero-offset adjustments.
Dual-slope converter accuracy is unrelated to the inte-
grating resistor and capacitor values, as long as they are
stable during a measurement cycle. By converting the
unknown analog input voltage into an easily-measured
function of time, the dual-slope converter reduces the need
for expensive, precision passive components.
Noise immunity is an inherent benefit of the integrating
conversion method. Noise spikes are integrated, or aver-
aged, to zero during the integration period. Integrating ADCs
are immune to the large conversion errors that plague
successive approximation converters in high-noise environ-
ments.
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
1
RC 0
40
V
DD
16 BUSY
8 DB7
9 DB6
10 DB5
11 DB4
12 DB3
13 DB2
14 DB1
20
DGND
22
V
SS
+ 32
IN
–
IN
100 MΩ
0.01
µF
INPUT
+1.6384V
15 DB0
1 CS
2 CE
3 WR
4 RD
5 CONT/DEMAND
6 OVR/POL
7 L/H
17
OSC1
61.44 kHz
**
18
OSC2
COMP
31
COMMON 30
+
REF1 39
+ 33
REF2
36
REF–
+
CREF1 38
TC850
–
CREF1 37
+
CREF2 34
–
CREF2 35
BUFFER
INTIN
INTOUT
25
24
23
+0.0265V
1
µF
*
1
µF
*
120 MΩ
RINT
0.1µF
CINT
TEST
19
NC
∫
t
SI
V
IN
(t) dt =
V
R
t
RI
,
RC
**
21
CINTA CINTBCBUFA CBUFB
28
0.1
µF
0.1
µF
29
0.1
µF
27
0.1
µF
26
0.1
µF
where: V
R
= Reference voltage
t
SI
= Signal integration time (fixed)
t
RI
= Reference voltage integration time (variable).
NOTES:
Unless otherwise specified, all 0.1µF capacitors are film dielectric.
Ceramic capacitors are not recommended.
NC = No internal capacitors
*Polypropylene capacitors.
** 100pF Mica capacitors.
Figure 1. Standard Circuit Configuration
8
3-81
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