15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
SIGNAL
INTEGRATE
REFERENCE
DEINTEGRATE
END OF
CONVERSION
AUTO
INTEGRATOR ZERO
OUTPUT
TIME
0V
additional 6 bits of resolution. The result is 15 bits of
resolution achieved with only 2
9
+ 2
6
(512 + 64, or 576) clock
pulses for deintegration. A complete conversion cycle occu-
pies only 1280 clock pulses.
In order to generate "fast-slow" integration phases, two
voltage references are required. The primary reference
(V
REF1
) is set to one-half of the full-scale voltage (typically
V
REF1
= 1.6384V, and V
FS
= 3.2768V). The secondary
voltage reference (V
REF2
) is set to V
REF1
/64 (typically 25.6
mV). To maintain 15-bit linearity, a tolerance of 0.5% for
V
REF2
is recommended.
Figure 2A. Dual-Slope ADC Cycle
ANALOG SECTION DESCRIPTION
The TC850 analog section consists of an input buffer
amplifier, integrator amplifier, comparator, and analog
switches. A simplified block diagram is shown in Figure 3.
"FAST" REFERENCE
DEINTEGRATE
(9-BIT RESOLUTION)
"SLOW" REFERENCE
DEINTEGRATE
(6-BIT RESOLUTION)
Conversion Timing
SIGNAL
INTERGRATE
END OF
CONVERSION
INTEGRATOR
OUTPUT
AUTO
ZERO
TIME
0V
Each conversion consists of three phases: (1) Zero
Integrator, (2) Signal Integrate, and (3) Reference Integrate
(or Deintegrate). Each conversion cycle requires 1280 inter-
nal clock cycles (Figure 4).
Figure 2B. "Fast-Slow" Reference Deintegrate Cycle
CREF1
REF1+
C+
REF1
DE
REF1–
–
C REF2
–
C REF1
DE
C REF2
REF2+
–
C REF2
BUFF
RINT
CINT
INTIN
INTOUT
DE
DE
–
+
INTEGRATOR*
–
BUFFER*
+
–
+
COMPARATOR*
Z1
TO
DIGITAL
SECTION
+
IN
INT
DE1
(–)
DE1
(+)
DE1
(–)
DE1
(+)
DE1
(+)
COMMON
–
IN
INT
INT
DE1
(–)
DE2
(+)
DE2
(–)
*AUTO-ZEROED
AMPLIFIERS
TC850
Figure 3. Analog Section Simplified Schematic
3-82
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
