DG417/418/419
Test Circuits
V
O
is the steady state output with the switch on.
+5 V
+15 V
Logic
Input
V
L
"10
V
S
IN
GND
V–
V+
D
3V
50%
0V
V
O
R
L
300
W
C
L
35 pF
Switch
Input
V
S
V
O
90%
t
OFF
t
r
<20 ns
t
f
<20 ns
–15 V
C
L
(includes fixture and stray capacitance)
V
O
= V
S
R
L
R
L
+ r
DS(on)
Switch
Output
0V
t
ON
Note: Logic input waveform is inverted for switches that have
the opposite logic sense.
Figure 2.
Switching Time (DG417/418)
+5 V
+15 V
Logic
Input
V
L
V
S1
V
S2
S
1
S
2
IN
GND
V–
R
L
300
W
C
L
35 pF
V+
D
V
O
V
S1
= V
S2
V
O
Switch
Output
C
L
(includes fixture and stray capacitance)
–15 V
0V
t
D
t
D
3V
0V
t
r
<20 ns
t
f
<20 ns
90%
Figure 3.
Break-Before-Make (DG419)
+5 V
V
L
V
S1
V
S2
S
1
S
2
IN
GND
V–
V+
+15 V
Logic
Input
3V
50%
0V
t
TRANS
V
S1
V
01
Switch
Output
V
S2
V
02
10%
t
TRANS
90%
t
r
<20 ns
t
f
<20 ns
D
V
O
R
L
300
W
C
L
35 pF
–15 V
C
L
(includes fixture and stray capacitance)
V
O
= V
S
R
L
R
L
+ r
DS(on)
Figure 4.
Transition Time (DG419)
Siliconix
S-52880—Rev. D, 28-Apr-97
7
TEMIC [ TEMIC SEMICONDUCTORS ]
