TS80C31X2-VCBR 参数 Datasheet PDF下载

TS80C31X2

6.3 TS80C31X2 Serial I/O Port

The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.

It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous

Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and

reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

q

q

Framing error detection

Automatic address recognition

6.3.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing

bit error detection feature, set SMOD0 bit in PCON register (See Figure 4).

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD = 1)

SM0 to UART mode control (SMOD = 0)

SMOD1 SMOD0

-

POF

GF1

GF0

PD

IDL

PCON (87h)

To UART framing error control

Figure 4. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop

bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit

is not found, the Framing Error bit (FE) in SCON register (See Table 5.) bit is set.

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Rev. A - Mar. 19, 1999

Preliminary