TS80C31X2
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 5. and Figure 6.).
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Start
bit
RI
SMOD0=X
FE
SMOD0=1
Data byte
Stop
bit
Figure 5. UART Timings in Mode 1
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Data byte
Ninth Stop
bit bit
Figure 6. UART Timings in Modes 2 and 3
6.3.2 Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled
(SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
Rev. A - Mar. 19, 1999
13
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
