Data Sheet 71M6531D/F-71M6532D/F
Table 22:
TMOD
Register Bit Description (SFR 0x89)
Bit
Symbol
Timer/Counter 1:
Gate
TMOD[7]
Function
FDS 6531/6532 005
TMOD[6]
C/T
TMOD[5:4]
M1:M0
If set, enables external gate control (pin INT1). When INT1 is high and
the
TR1
bit is set (see the
TCON
register), a counter is incremented every
falling edge on T1 input pin
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as a
timer.
Selects the mode for Timer/Counter 0 as shown in
Timer/Counter 0:
TMOD[3]
Gate
TMOD[2]
C/T
TMOD[1:0]
M1:M0
If set, enables external gate control (pin INT0). When INT0 is high and
the
TR0
bit is set (see the
TCON
register), a counter is incremented every
falling edge on T0 input pin.
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as
a timer.
Selects the mode for Timer/Counter 1, as shown in
Table 23: The
TCON
Register Bit Functions (SFR 0x88)
Bit
TCON[7]
Symbol
TF1
TCON[6]
TCON[5]
TR1
TF0
TCON[4]
TCON[3]
TCON[2]
TCON[1]
TCON[0]
TR0
IE1
IT1
IE0
IT0
Function
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
Timer 1 run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This
flag can be cleared by software and is automatically cleared when an
interrupt is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on exter-
nal pin int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level
on input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on exter-
nal pin int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level
on input pin to cause interrupt.
1.4.8
WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard watchdog timer instead (see
1.4.9
Interrupts
The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON,
IRCON
and
SCON).
Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs
IEN0, IEN1
and
IEN2.
shows the device interrupt structure.
30
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