Data Sheet 71M6531D/F-71M6532D/F
Interrupt Enable
Name
Location
Interrupt Flag
Name
Location
IE_FWCOL1
SFR E8[2]
IE_PLLRISE
SFR E8[6]
IE_PLLFALL
SFR E8[7]
IE_WAKE
SFR E8[5]
IE_PB
SFR E8[4]
FDS 6531/6532 005
Interrupt Description
FWCOL1 interrupt (INT 2)
PLL_OK rise interrupt (INT 4)
PLL_OK fall interrupt (INT 4)
AUTOWAKE flag
PB flag
EX_PLL
2007[5]
The
AUTOWAKE
and
PB
flag bits are shown in
because they behave similarly to interrupt flags,
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in
Table 32: Interrupt Priority Level Groups
Group
0
1
2
3
4
5
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
–
Group Members
Serial channel 1 interrupt
–
–
External interrupt 2
–
–
–
–
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
by setting or clearing one bit in the SFR interrupt priority register
IP0
and one in
IP1(Table
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
IP1[x]
0
0
1
1
IP0[x]
0
1
0
1
Priority Level
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Table 34: Interrupt Priority Registers (IP0 and
IP1)
Register
IP0
IP1
Address
SFR 0xA9
SFR 0xB9
Bit 7
(MSB)
–
–
Bit 6
–
–
Bit 5
IP0[5]
IP1[5]
Bit 4
IP0[4]
IP1[4]
Bit 3
IP0[3]
IP1[3]
Bit 2
IP0[2]
IP1[2]
Bit 1
IP0[1]
IP1[1]
Bit 0
(LSB)
IP0[0]
IP1[0]
34
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