FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Table 13: Stretch Memory Cycle Width
CKCON[2:0]
000
001
010
011
100
101
110
111
Stretch
Value
0
1
2
3
4
5
6
7
Read signal width
memaddr
memrd
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Write signal width
memaddr
memwr
2
1
3
1
4
2
5
3
6
4
7
5
8
6
9
7
1.4.4
Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
shows the location and description of the SFRs specific to the 71M6531D/F and 71M6532D/F.
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs
Register
(Alternate
Name)
EEDATA
EECTRL
SFR
Address
0x9E
0x9F
Bit Field
Name
R/W
R/W
R/W
Description
I
2
C EEPROM interface data register.
I
2
C EEPROM interface control register. See
Section
for a descrip-
tion of the command and status bits available
for
EECTRL.
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the
section for details.
Flash Bank Selection.
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase
cycle.
Program Write Enable:
0: MOVX commands refer to XRAM Space,
normal operation (default).
1: MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
Mass Erase Enable:
0: Mass Erase disabled (default).
1: Mass Erase enabled.
Must be re-written for each new Mass Erase
cycle.
Enables security provisions that prevent exter-
nal reading of flash memory and CE program
RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
Indicates that the preboot sequence is active.
ERASE
(FLSH_ERASE)
FL_BANK
PGADDR
(FLSH_PGADR)
0x94
W
0xB6[2:0]
0xB7
R/W
R/W
FLSHCRL
0xB2[0]
FLSH_PWE
R/W
0xB2[1]
FLSH_MEEN
W
0xB2[6]
SECURE
R/W
0xB2[7]
PREBOOT
R
v1.2
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25
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