71M6532D-IGT/F 参数 Datasheet PDF下载

FDS 6531/6532 005

Data Sheet 71M6531D/F-71M6532D/F

When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM

will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should

then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to

a low-Z state.

EECTRL Byte Written

CNT Cycles (6 shown)

Write -- No HiZ

SCLK (output)

SDATA (output)

SDATA output Z

BUSY

(bit)

D7

D6

D5

(LoZ)

D4

D3

D2

INT5

Figure 11: 3-Wire Interface. Write Command, HiZ=0.

EECTRL Byte Written

CNT Cycles (6 shown)

Write -- With HiZ

SCLK (output)

SDATA (output)

SDATA output Z

BUSY

(bit)

D7

D6

D5

(LoZ)

D4

D3

D2

INT5

(HiZ)

Figure 12: 3-Wire Interface. Write Command, HiZ=1

EECTRL Byte Written

CNT Cycles (8 shown)

READ

SCLK (output)

SDATA (input)

SDATA output Z

BUSY

(bit)

D7

D6

(HiZ)

D5

D4

D3

D2

D1

D0

INT5

Figure 13: 3-Wire Interface. Read Command.

EECTRL Byte Written

Write -- No HiZ

SCLK (output)

SDATA (output)

SDATA output Z

BUSY

(bit)

INT5 not issued

CNT Cycles (0 shown)

EECTRL Byte Written

Write -- HiZ

SCLK (output)

INT5 not issued

CNT Cycles (0 shown)

D7

(LoZ)

SDATA (output)

SDATA output Z

BUSY

(bit)

(HiZ)

Figure 14: 3-Wire Interface. Write Command when CNT=0

v1.2

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