FDS 6531/6532 005
SERIAL READ
8 bit CMD
16 bit Address
Data Sheet 71M6531D/F-71M6532D/F
DATA[ADDR]
DATA[ADDR+1]
PCSZ
0
PSCK
(From Host) PSDI
(From 6531) PSDO
x
C7
C6
C5
C0
HI Z
A15
A14
A1
A0
x
D7
D6
D1
D0
D7
7
8
23
24
31
32
Extended Read . . .
39
D6
D1
D0
SERIAL WRITE
8 bit CMD
16 bit Address
DATA[ADDR]
DATA[ADDR+1]
PCSZ
0
PSCK
(From Host) PSDI
(From 6531) PSDO
x
C7
C6
C5
C0
A15
A14
A1
A0
HI Z
D7
D6
D1
D0
D7
7
8
23
24
31
32
Extended Write . . .
39
D6
D1
D0
x
Figure 16: SPI Slave Port: Typical Read and Write operations
Possible applications for the SPI interface are:
1) An external host reads data from CE locations to obtain metering information. This can be used
in applications where the 71M6531D/F or 71M6532D/F function as smart front-ends with prepro-
cessing capability. Since the addresses are in 16-bit format, any type of XRAM data can be ac-
cessed: CE, MPU, I/O RAM, but not SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory loca-
tions, the external host can initiate and control processes in the MPU of the 71M6531D/F or
71M6532D/F. Writing to a CE or MPU location normally generates an interrupt, a function that
can be used to signal to the MPU that the byte that had just been written by the external host
must be read and processed. Data can also be inserted by the external host without generating
an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses
the 71M6531D/F or 71M6532D/F as an analog front-end (AFE).
1.5.16 Hardware Watchdog Timer
V1
V3P3
V3P3 - 10mV
V3P3 -
400mV
Normal
operation,
WDT
enabled
VBIAS
WDT dis-
abled
An independent, robust, fixed-duration, watchdog timer (WDT) is included
in the 71M6531D/F and 71M6532D/F. It uses the RTC crystal oscillator as
its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not refreshed on time, the WDT overflows and the part
is reset as if the RESET pin were pulled high, except that the I/O RAM bits
will be in the same state as after a wake-up from SLEEP or LCD modes
(see the I/O RAM description in Section
for a list of I/O RAM bit states
after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after the
WDT overflow, the MPU will be launched from program address 0x0000.
A status bit,
WD_OVF,
is set when the WDT overflow occurs. This bit is
powered by the nonvolatile supply and can be read by the MPU when
WAKE rises to determine if the part is initializing after a WDT overflow
event or after a power-up. After it is read, the MPU firmware must clear
WD_OVF.
The
WD_OVF
bit is also cleared by the RESET pin.
There is no internal digital state that deactivates the WDT.
Battery
modes
0V
Figure 17: Functions defined by V1
The WDT can be disabled by tying the V1 pin to V3P3 (see Figure 17). Of course, this also deactivates
V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
51
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
