Data Sheet 71M6531D/F-71M6532D/F
Status
Bit
3:0
Name
CMD[3:0]
Read/
Write
W
Reset
State
0000
Polarity
Positive
Description
CMD[3:0]
0000
FDS 6531/6532 005
0010
0011
0101
0110
1001
Others
Operation
No-op command. Stops the I
2
C
clock (SCK, DIO4). If not issued,
SCK keeps toggling.
Receive a byte from the EEPROM
and send ACK.
Transmit a byte to the EEPROM.
Issue a STOP sequence.
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the
ERROR
bit.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In
this case, a resistor has to be used in series with SDA to avoid data collisions due to limits in the
speed at which the SDA pin can be switched from output to input. Controlling DIO4 and DIO5 di-
rectly is discouraged, because it may tie up the MPU to the point where it may become too busy to pro-
cess interrupts.
Three-Wire (µ-Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA, SCK and a DIO pin for CS is available. The interface is
selected by setting
DIO_EEX
= 2 (b10). The
EECTRL
bits when the three-wire interface is selected are
shown in
EECTRL
is written, up to 8 bits from
EEDATA
are either written to the EEPROM
or read from the EEPROM, depending on the values of the
EECTRL
bits.
The µ-Wire EEPROM interface is only functional when
MPU_DIV[2:0]
= 000.
Table 44:
EECTRL
Bits for the 3-Wire Interface
Control
Bit
7
Name
WFR
Read/
Write
W
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be de-
layed until a rising edge is seen on the data line. This bit can be used
during the last byte of a Write command to cause the INT5 interrupt to
occur when the EEPROM has finished its internal write sequence. This
bit is ignored if HiZ = 0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immedi-
ately after the last SCK rising edge.
Indicates that
EEDATA
is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first and right
justified into the low order bits of
EEDATA.
If RD=0, CNT bits will be
sent MSB first to the EEPROM, shifted out of the MSB of
EEDATA.
If
CNT[3:0]
is zero, SDATA will simply obey the HiZ bit.
6
5
4
3:0
BUSY
HiZ
RD
CNT[3:0]
R
W
W
W
The timing diagrams in
through
describe the 3-wire EEPROM interface behavior. All
commands begin when the
EECTRL
register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in
through
are then sent via
EECTRL
and
EEDATA.
48
© 2005-2009 TERIDIAN Semiconductor Corporation
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
