欢迎访问ic37.com |
会员登录 免费注册
发布采购

71M6532F-IGT/F 参数 Datasheet PDF下载

71M6532F-IGT/F图片预览
型号: 71M6532F-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用: 电源电路电源管理电路
文件页数/大小: 115 页 / 2363 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号71M6532F-IGT/F的Datasheet PDF文件第73页浏览型号71M6532F-IGT/F的Datasheet PDF文件第74页浏览型号71M6532F-IGT/F的Datasheet PDF文件第75页浏览型号71M6532F-IGT/F的Datasheet PDF文件第76页浏览型号71M6532F-IGT/F的Datasheet PDF文件第78页浏览型号71M6532F-IGT/F的Datasheet PDF文件第79页浏览型号71M6532F-IGT/F的Datasheet PDF文件第80页浏览型号71M6532F-IGT/F的Datasheet PDF文件第81页  
FDS 6531/6532 005  
Data Sheet 71M6531D/F-71M6532D/F  
Description  
Name  
Location  
Reset Wake  
Dir  
DIO_EEX[1:0]  
2008[7:6]  
0
0
R/W When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 be-  
comes SDCK and DIO5 becomes bi-directional SDATA.  
DIO_EEX[1:0]  
Function  
00  
01  
10  
11  
Disable EEPROM interface  
2-Wire EEPROM interface  
3-Wire EEPROM interface  
not used  
DIO_PV  
2008[2]  
2008[3]  
200F[3]  
200F[2]  
SFR 9E  
SFR 9F  
2005[5]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W Causes VARPULSE to be output on DIO7.  
R/W Causes WPULSE to be output on DIO6.  
R/W Causes XPULSE to be output on DIO8.  
R/W Causes YPULSE to be output on DIO9.  
R/W Serial EEPROM interface data.  
DIO_PW  
DIO_PX  
DIO_PY  
EEDATA[7:0]  
EECTRL[7:0]  
ECK_DIS  
R/W Serial EEPROM interface control.  
R/W Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.  
If ECK_DIS is set, the emulator and programming devices will be unable to  
erase or program the device.  
EQU[2:0]  
2000[7:5]  
0
0
R/W Specifies the power equation to be used by the CE.  
EX_XFR  
EX_RTC  
EX_FWCOL  
EX_PLL  
2002[0]  
2002[1]  
2007[4]  
2007[5]  
0
0
0
0
0
0
0
0
R/W Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-  
WareCollision (FWCOL) and PLL interrupts. Note that if one of these interrupts is to  
be enabled, its corresponding MPU EX enable must also be set. See Section 1.4.9  
Interrupts for details.  
FIR_LEN[1:0]  
2007[3:2]  
1
1
R/W FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore con-  
trols the time taken for each conversion.  
Resulting FIR  
Filter Cycles  
Resulting  
CK32 Cycles DC Gain  
Resulting  
[M40MHZ, M26MHZ] FIR_LEN  
[00], [10], or [11]  
00  
01  
10  
00  
01  
10  
138  
288  
384  
186  
384  
588  
1
2
3
1
2
3
0.110017  
1.000  
2.37037  
0.113644  
1.000  
[01]  
3.590363  
FL_BANK[2:0]  
SFR B6[2:0]  
1
1
R/W Flash bank. Memory above 32 KB is mapped to the MPU address space from 0x8000  
to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in flash is  
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.  
v1.2  
© 2005-2009 TERIDIAN Semiconductor Corporation  
77