73M1903C-IMR/F 参数 Datasheet PDF下载

73M1903C

Modem Analog Front End

DATA SHEET

List of Figures

Figure 1: SCLK and

FS

with SckMode=0..................................................................................................

7

Figure 2: Control frame position vs. SPOS

.............................................................................................. 7

Figure 3: Serial Port Timing Diagrams......................................................................................................

8

Figure 4: 73M1903C Host connection in master and slave mode ................................................................ 9

Figure 5: 73M1903C Daisy chaining for master/slave mode and slave modes

.................................... 9

Figure 6: Clock Generation ......................................................................................................................... 17

Figure 7: Analog block diagram .................................................................................................................. 20

Figure 8: Overall TX path frequency response at 8kHz sample rate.......................................................... 21

Figure 9: Frequency response of TX path for DC to 4kHz in band signal at 8kHz sample rate........

22

Figure 10: Overall receiver frequency response at 8kHz sample rate.................................................

25

Figure 11: Rx passband response at 8kHz sample rate........................................................................

26

Figure 12: RXD Spectrum of 1kHz tone

.................................................................................................. 27

Figure 13: RXD Spectrum of 0.5kHz, 1kHz, 2kHz, 3kHz and 3.5kHz tones of Equal Amplitudes......

27

Figure 14: Serial Port Data Timing

.......................................................................................................... 31

Figure 15: Typical DAA block diagram........................................................................................................ 37

Figure 16: Single transmitter arrangement ................................................................................................. 38

Figure 17: Dual transmitter arrangement .................................................................................................... 39

Figure 18: NCO block diagram ................................................................................................................... 40

Figure 19: PLL Block Diagram .................................................................................................................... 41

Page: 3 of 46

©

2005-2008 TERIDIAN Semiconductor Corporation

Rev 4.3