73M1903C
Modem Analog Front End
DATA SHEET
MODEM ANALOG FRONT END (MAFE) SERIAL INTERFACE
The MAFE (Modem Analog Front End) serial data port is a bi-directional port that can be supported by
most DSPs. The typical I
2
S (Inter-IC Sound, NXP semiconductor) bus can be easily converted into MAFE
compatible interface. The 73M1903C can be configured either as a master or a slave of the serial
interface. When the 73M1903C is configured as a master device, it generates a serial bit clock, Sclk,
from a system clock, Sysclk, which is normally an output from an on-chip PLL that can be programmed by
the user. In master mode, the serial bit clock is always derived by dividing the system clock by 18. The
Sclk rate, Fsclk, is related to the frame synchronization rate (sample rate), Fs, by the relationship Fsclk =
256 x Fs or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is
also the rate at which both transmit and receive data bytes are sent (received) to (by) the Host.
Throughout this document two pairs of sample rate, Fs, and crystal frequency, Fxtal, will be often cited to
facilitate discussions. They are:
1. Fxtal
1
= 27MHz, Fs
1
= 7.2kHz
2. Fxtal
2
= 18.432MHz, Fs
2
= 8kHz.
3. Fxtal
3
= 24.576MHz, Fs
3
= 9.6kHz
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal
1
= 27.000MHz, then sclk=1.500MHz and Fs=sclk/256 = 5.859375kHz.
2. If Fxtal
2
= 18.432MHz, then sclk=1.024MHz and Fs=sclk/256 = 4.00kHz.
3. If Fxtal
3
= 24.576MHz, then sclk=1.3653MHz and Fs=sclk/256 = 5.33kHz.
When 73M1903C is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs
1
= 7.2kHz, Fsys = 4608 * Fs = 33.1776MHz and sclk = Fsys / 18 = 1.8432MHz.
2. If Fs
2
= 8.0kHz, Fsys = 4608 * Fs = 36.8640MHz and sclk = Fsys / 18 = 2.048MHz.
3. If Fs
3
= 9.6kHz, Fsys = 4608 * Fs = 44.2368MHz and sclk = Fsys / 18 = 2.4576MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting Frcvco bit
(Bit 7 in Register0E). The transition should be forced on or after the second frame synch period following
the write to a designated PLL programming registers (Register08 to Register0D).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing ENFE bit (bit 7 Register00).
During the normal operation, a data frame sync signal (FS) is generated by the 73M1903C at the rate of
Fs. For every data
FS
there are 16 bits transmitted and 16 bits received. The frame synchronization (FS)
signal is pin programmable for type.
FS
can either be early or late determined by the state of the TYPE
input pin. When Type pin is left open, an early
FS
is generated in the bit clock prior to the first data bit
transmitted or received. When held low, a late
FS
operates as a chip select; the
FS
signal is active for all
bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active and
ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines the
frame synchronization mode used.
Page: 5 of 46
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2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
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