73M1903C
Modem Analog Front End
DATA SHEET
SERIAL DATA AND CONTROL
The bits transmitted on the SDOUT pin are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
If the HC bit (Bit 0 of Register01) is set to zero, the 16 bits that are received on the SDIN are defined as
follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4
In this case LSB(TX0) in a transmit bit stream is forced to 0 automatically.
bit3
TX3
bit2
TX2
bit1
TX1
bit0
CTL
If the Hardware Control bit (Bit 0 of Register 01) is set to one, the 16 bits that are received on the SDIN
input are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9
TX15 TX14 TX13 TX12 TX11 TX10 TX9
bit8
TX8
bit7
TX7
bit6
TX6
bit5
TX5
bit4
TX4
bit3
TX3
bit2
TX2
bit1
TX1
bit0
TX0
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit
code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data
frames. If the hardware control bit is set to zero, CTL is used by software to request a control frame. If
CTL is high, a control frame will be initiated before the next data frame. A control frame allows the
controller to read or write status and control to the 73M1903C.
The control word received on the SDIN pin is defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10
R/W A6
A5
A4
A3
A2
bit9
A1
bit8
A0
bit7
D7
bit6
D6
bit5
D5
bit4
D4
bit3
D3
bit2
D2
bit1
D1
bit0
D0
The control word transmitted on the SDOUT pin is defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10
0
0
0
0
0
0
bit9
0
bit8
0
bit7
D7
bit6
D6
bit5
D5
bit4
D4
bit3
D3
bit2
D2
bit1
D1
bit0
D0
If the R/W bit (Bit15 of control word) is set to a 0, the data byte transmitted on the SDOUT pin is all zeros
and the data received on the SDIN pin is written to the register pointed to by the received address bits;
A6-A0. If the R/W bit is set to a 1, there is no write to any register and the data byte transmitted on the
SDOUT pin is the data contained in the register pointed to by address bits A6-A0. Only one control frame
can occur between any two data frames.
Writes to unimplemented registers are ignored. Reading an unimplemented register returns an unknown
value. The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is
set to a 0 the control frames occur mid way between data frames, i.e., the time between data frames is
equal. If SPOS is set to a 1, the control frame is ¼ of the way between consecutive data frames, i.e., the
control frame is closer to the first data frame. This is illustrated in Figure 2.
The TERIDIAN 73M1903C modem AFE IC includes a feature that shuts off the serial clock (SCLK) after
32 cycles of SCLK following the frame synch (figure 1). The SckMode pin controls this mode. If this pin
is left open the clock will run continuously. If SckMode is set low, the clock will be gated on for 32 clocks
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2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
