DS_6612_001
78M6612 Data Sheet
1.5.7 Digital I/O
The device includes up to 18 pins (QFN 68 package) or 16 pins (LQFP 64 package) of general purpose
digital I/O. These pins are compatible with 5V inputs (no current-limiting resistors are needed). Some of
them are dedicated DIO (DIO3), some are dual-function that can alternatively be used as LCD drivers
(DIO4-11, 14-17, 19-21) and some share functions with the optical port (DIO1, DIO2). On reset or
power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control.
The pins are configured by the DIO registers and by the five bits of the
LCD_NUM
register (located in I/O
RAM). Once declared as DIO, each pin can be configured independently as an input or output with the
DIO_DIRn
bits. A 3-bit configuration word,
DIO_Rx,
can be used for certain pins, when configured as
DIO, to individually assign an internal resource such as an interrupt or a timer control.
lists the
direction registers and configurability associated with each group of DIO pins.
shows the con-
figuration for a DIO pin through its associated bit in its
DIO_DIR
register.
Tables showing the relationship between
LCD_NUM
and the available segment/DIO pins can be found in
the Applications section and in
under
LCD_NUM[4:0].
Table 38: Data/Direction Registers and Internal Resources for DIO Pin Groups
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
x
–
–
–
–
–
1
5
7
6
0
1
1
2
3
3
2
2
3
–
5
3
–
3
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
5
6
7
0
1
4
3
6
3
9
4
5
3
7
4
0
5
6
3
8
4
1
6
7
3
9
4
2
7
8
4
0
4
3
0
9
4
1
4
4
1
1
0
4
2
4
5
2
2
1
1
4
3
4
6
3
3
1
2
–
–
–
–
1
3
–
–
–
–
1
4
2
0
2
1
6
6
1
5
2
1
2
2
7
7
DIO1=P1
(SFR 0x90)
DIO_DIR1
(SFR 0x91)
Y
Y
–
–
–
–
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
16
22
23
0
0
1
7
1
2
1
3
1
1
1
8
–
–
–
–
1
9
2
3
2
4
3
3
2
0
4
4
4
7
4
4
2
1
–
6
8
5
5
2
2
–
2
3
–
–
–
–
–
DIO2=P2
(SFR 0xA0)
DIO_DIR2
(SFR 0xA1)
N
N
–
N
N
N
–
–
Rev. 1.2
43
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