ADC12D1000, ADC12D1600
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SNAS480M –MAY 2010–REVISED MARCH 2013
Table 2. Control and Status Balls (continued)
Ball No.
Name
Equivalent Circuit
Description
V
A
100 kW
Serial Data-In. In ECM, serial data is shifted into
the device on this pin while SCS signal is asserted
(logic-low).
B4
SDI
GND
V
A
Serial Data-Out. In ECM, serial data is shifted out
of the device on this pin while SCS signal is
asserted (logic-low). This output is at TRI-STATE
when SCS is de-asserted.
A3
SDO
GND
Do Not Connect. These pins are used for internal
purposes and should not be connected, i.e. left
floating. Do not ground.
D1, D7, E3, F4,
W3, U7
DNC
NC
NONE
NONE
Not Connected. This pin is not bonded and may
be left floating or connected to any potential.
C7
Table 3. Power and Ground Balls
Ball No.
Name
Equivalent Circuit
Description
A2, A6, B6, C6,
D8, D9, E1, F1,
H4, N4, R1, T1,
U8, U9, W6, Y2,
Y6
Power Supply for the Analog circuitry. This supply
is tied to the ESD ring. Therefore, it must be
powered up before or with any other supply.
VA
NONE
G1, G3, G4, H2,
J3, K3, L3, M3,
N2, P1, P3, P4,
R3, R4
Power Supply for the Track-and-Hold and Clock
circuitry.
VTC
NONE
NONE
A11, A15, C18,
D11, D15, D17,
J17, J20, R17,
R20, T17, U11,
U15, U16, Y11,
Y15
VDR
Power Supply for the Output Drivers.
Power Supply for the Digital Encoder.
A8, B9, C8, V8,
W9, Y8
VE
NONE
NONE
Bias Voltage I-channel. This is an externally
decoupled bias voltage for the I-channel. Each pin
should individually be decoupled with a 100 nF
capacitor via a low resistance, low inductance
path to GND.
J4, K2
L2, M4
VbiasI
Bias Voltage Q-channel. This is an externally
decoupled bias voltage for the Q-channel. Each
pin should individually be decoupled with a 100 nF
capacitor via a low resistance, low inductance
path to GND.
VbiasQ
NONE
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