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ADC12D1600 参数 Datasheet PDF下载

ADC12D1600图片预览
型号: ADC12D1600
PDF下载: 下载PDF文件 查看货源
内容描述: ADC12D1000 / ADC12D1600 12位, 2.0 / 3.2 GSPS超高速ADC [ADC12D1000/ADC12D1600 12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC]
分类和应用:
文件页数/大小: 73 页 / 1626 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADC12D1000, ADC12D1600  
SNAS480M MAY 2010REVISED MARCH 2013  
www.ti.com  
Table 1. Analog Front-End and Clock Balls (continued)  
Ball No.  
Name  
Equivalent Circuit  
Description  
V
A
Reference Clock Input. When the AutoSync  
feature is active, and the ADC12D1000/1600 is in  
Slave Mode, the internal divided clocks are  
synchronized with respect to this input clock. The  
delay on this clock may be adjusted when  
synchronizing multiple ADCs. This feature is  
available in ECM via Control Register (Addr: Eh).  
50k  
50k  
AGND  
Y4/W5  
RCLK+/-  
100  
V
BIAS  
V
A
AGND  
V
A
Reference Clock Output 1 and 2. These signals  
provide a reference clock at a rate of CLK/4, when  
enabled, independently of whether the ADC is in  
Master or Slave Mode. They are used to drive the  
RCLK of another ADC12D1000/1600, to enable  
automatic synchronization for multiple ADCs  
(AutoSync feature). The impedance of each trace  
from RCOut1 and RCOut2 to the RCLK of another  
ADC12D1000/1600 should be 100Ω differential.  
Having two clock outputs allows the auto-  
100W  
100W  
Y5/U6  
V6/V7  
RCOut1+/-  
RCOut2+/-  
-
+
synchronization to propagate as a binary tree. Use  
the DOC Bit (Addr: Eh, Bit 1) to enable/ disable  
this feature; default is disabled.  
A GND  
Table 2. Control and Status Balls  
Ball No.  
Name  
Equivalent Circuit  
Description  
Dual Edge Sampling (DES) Mode select. In the  
Non-Extended Control Mode (Non-ECM), when  
this input is set to logic-high, the DES Mode of  
operation is selected, meaning that the VinI input  
is sampled by both channels in a time-interleaved  
manner. The VinQ input is ignored. When this  
input is set to logic-low, the device is in Non-DES  
Mode, i.e. the I- and Q-channels operate  
V
A
V5  
DES  
independently. In the Extended Control Mode  
(ECM), this input is ignored and DES Mode  
selection is controlled through the Control Register  
by the DES Bit (Addr: 0h, Bit 7); default is Non-  
DES Mode operation.  
GND  
V
A
Calibration Delay select. By setting this input logic-  
high or logic-low, the user can select the device to  
wait a longer or shorter amount of time,  
respectively, before the automatic power-on self-  
calibration is initiated. This feature is pin-controlled  
only and is always active during ECM and Non-  
ECM.  
V4  
CalDly  
GND  
6
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Product Folder Links: ADC12D1000 ADC12D1600