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ADC12D1600 参数 Datasheet PDF下载

ADC12D1600图片预览
型号: ADC12D1600
PDF下载: 下载PDF文件 查看货源
内容描述: ADC12D1000 / ADC12D1600 12位, 2.0 / 3.2 GSPS超高速ADC [ADC12D1000/ADC12D1600 12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC]
分类和应用:
文件页数/大小: 73 页 / 1626 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADC12D1000, ADC12D1600  
www.ti.com  
SNAS480M MAY 2010REVISED MARCH 2013  
Table 2. Control and Status Balls (continued)  
Ball No.  
Name  
Equivalent Circuit  
Description  
Calibration cycle initiate. The user can command  
the device to execute a self-calibration cycle by  
holding this input high a minimum of tCAL_H after  
having held it low a minimum of tCAL_L. If this input  
is held high at the time of power-on, the automatic  
power-on calibration cycle is inhibited until this  
input is cycled low-then-high. This pin is active in  
both ECM and Non-ECM. In ECM, this pin is  
logically OR'd with the CAL Bit (Addr: 0h, Bit 15)  
in the Control Register. Therefore, both pin and bit  
must be set low and then either can be set high to  
execute an on-command calibration.  
V
A
D6  
CAL  
GND  
V
A
Calibration Running indication. This output is  
logic-high while the calibration sequence is  
executing. This output is logic-low otherwise.  
B5  
CalRun  
GND  
V
V
V
A
Power Down I- and Q-channel. Setting either input  
to logic-high powers down the respective I- or Q-  
channel. Setting either input to logic-low brings the  
respective I- or Q-channel to an operational state  
after a finite time delay. This pin is active in both  
ECM and Non-ECM. In ECM, each Pin is logically  
OR'd with its respective Bit. Therefore, either this  
pin or the PDI and PDQ Bit in the Control Register  
can be used to power-down the I- and Q-channel  
(Addr: 0h, Bit 11 and Bit 10), respectively.  
50 kW  
U3  
V3  
PDI  
PDQ  
GND  
A
Test Pattern Mode select. With this input at logic-  
high, the device continuously outputs a fixed,  
repetitive test pattern at the digital outputs. In the  
ECM, this input is ignored and the Test Pattern  
Mode can only be activated through the Control  
Register by the TPM Bit (Addr: 0h, Bit 12).  
A4  
TPM  
GND  
A
Non-Demuxed Mode select. Setting this input to  
logic-high causes the digital output bus to be in  
the 1:1 Non-Demuxed Mode. Setting this input to  
logic-low causes the digital output bus to be in the  
1:2 Demuxed Mode. This feature is pin-controlled  
only and remains active during ECM and Non-  
ECM.  
A5  
NDM  
GND  
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