TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do
not
include delays by board routings. As a good
board design practice, such delays must
always
be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the
Using IBIS Models for Timing Analysis
application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 33 and Figure 15).
Figure 15 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 33. Board-Level Parameters Example (see Figure 15)
NO.
1
2
3
4
5
6
7
8
9
10
11
ECLKOUTx
(Output from DSP)
1
ECLKOUTx
(Input to External Device)
Control Signals†
(Output from DSP)
3
4
5
Control Signals
(Input to External Device)
Data Signals‡
(Output from External Device)
Data Signals‡
(Input to DSP)
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
6
7
8
2
DESCRIPTION
Clock route delay
Minimum DSP hold time
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
10
11
9
Figure 15. Board-Level Input/Output Timings
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