TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN for -600 devices
†‡§
(see Figure 16)
−600
NO.
1
2
3
4
5
tc(CLKIN)
tw(CLKINH)
tw(CLKINL)
tt(CLKIN)
Cycle time, CLKIN
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
PLL MODE x20
MIN
33.3
0.4C
0.4C
5
MAX
40
PLL MODE x12
MIN
20
0.4C
0.4C
5
MAX
23.8
PLL MODE x6
MIN
13.3
0.4C
0.4C
5
MAX
23.8
x1 (BYPASS)
MIN
0
0.45C
0.45C
1
0.02C
MAX
10
ns
ns
ns
ns
ns
UNIT
tJ(CLKIN)
Period jitter, CLKIN
0.02C
0.02C
0.02C
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡ For more details on the PLL multiplier factors (x6, x12, x20), see the
Clock PLL
section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
timing requirements for CLKIN for -720 devices
†‡§
(see Figure 16)
−720
NO.
1
2
3
4
5
tc(CLKIN)
tw(CLKINH)
tw(CLKINL)
tt(CLKIN)
Cycle time, CLKIN
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
PLL MODE x20
MIN
27.7
0.4C
0.4C
5
MAX
40
PLL MODE x12
MIN
16.6
0.4C
0.4C
5
MAX
23.8
PLL MODE x6
MIN
13.3
0.4C
0.4C
5
MAX
23.8
x1 (BYPASS)
MIN
0
0.45C
0.45C
1
0.02C
MAX
10
ns
ns
ns
ns
ns
UNIT
tJ(CLKIN)
Period jitter, CLKIN
0.02C
0.02C
0.02C
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡ For more details on the PLL multiplier factors (x6, x12, x20), see the
Clock PLL
section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
80
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
