tm
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
TE
CH
T15N1M16A
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SOJ
&
TSOP-II
48-Ball CSP
1
A
B
C
D
E
F
G
H
LB
TOP VIEW (Ball Down)
2
OE
3
A0
4
A1
5
A2
6
NC
I/O 9
UB
A3
A4
CE
I/O 1
I/O 1 0
I/O 1 1
A5
A6
I/O 2
I/O 3
VSS
I/O 1 2
NC
A7
I/O 4
VCC
VCC
I/O 1 3
NC
NC
I/O 5
VSS
I/O 1 5
I/O 1 4
A 14
A 15
I/O 6
I/O 7
I/O 1 6
NC
A 12
A 13
WE
I/O 8
NC
A8
A9
A 10
A 11
NC
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A15 Address inputs
I/O1~I/O16 Data inputs/outputs
CE
WE
OE
SYMBOL DESCRIPTIONS
LB
UB
Lower byte (I/O 1~8)
Upper byte (I/O 9~16)
Power supply
Ground
No connection
Publication Date: JUL . 2002
Revision: A
Chip enable
Write enable input
Output enable input
VCC
V
SS
NC
P. 2
TM Technology Inc. reserves the right
to change products or specifications without notice.
TMT [ TAIWAN MEMORY TECHNOLOGY ]
