TE
tmCH
T35L6432B
PIN DESCRIPTIONS
PINS
SYM.
TYPE
DESCRIPTION
Addresses: These inputs are registered and must meet the setup and
hold times around the rising edge of CLK. The burst counter
32-37, 44-49,
Input-
81, 82, 99, A0-A15
100,
Synchronous generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
Byte Writes: A byte write is LOW for a WRITE cyle and HIGH for
BW1
a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9-
Input-
BW2
93-96
DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-
Synchronous
BW3
BW4
DQ32. Data I/O are high impedance if either of these inputs are
LOW , conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte write operations
Input-
87
88
and must meet the setup and hold times around the rising edge of
BWE
GW
Synchronous
CLK.
Global Write: This active LOW input allows a full 32-bit WRITE to
Input-
occur independent of the BWE and BWn lines and must meet
Synchronous
the setup and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
Input-
writecontrol and burst control inputs on its rising edge. All
89
98
92
CLK
Synchronous synchronous inputs must meet setup and hold times around the
clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
Input-
the device and conditions internal use of ADSP. This input is
Synchronous
CE
sampled only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
Input-
the device. This input is sampled only when a new external address
Synchronous
CE2
is loaded. This input can be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to enable
Input-
97
CE2
the device. This input is sampled only when a new external address
Synchronous
is loaded. This input can be used for memory depth expansion.
Output enable: This active LOW asynchronous input enables the
86
83
Input
OE
data output drivers.
Address Advance: This active LOW input is used to control the
Input-
internal burst counter. A HIGH on this pin generates wait cycle
ADV
Synchronous
(no address advance).
Address Status Processor: This active LOW input, along withCE
Input-
84
being LOW, causes a new external address to be registered and a
Synchronous
ADSP
READ cycle is initiated using the new address.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: JUL. 2002
Revision: A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
