tm
Symbol
CLK
CKE
TE
CH
T4312816B
Description
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the output
registers.
Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
low synchronously with clock(set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen as
long as the CKE remains low. When all banks are in the idle state, deactivating the clock
controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Bank Select:
BA0,BA1 input select the bank for operation.
Pin Descriptions
(Table 1. Pin Details )
Type
Input
Input
BA0,BA1
Input
A0-A11
CS#
RAS#
CAS#
WE#
LDQM,
UDQM
DQ0-DQ15
NC/RFU
VDDQ
VSSQ
VDD
VSS
BA1
BA0
Select Bank
0
0
BANK #A
0
1
BANK #B
1
0
BANK #C
1
1
BANK #D
Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row address A0-
A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge)
to select one location out of the 2M available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The
address inputs also provide the op-code during a Mode Register Set command.
Input
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
Input
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction with
the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and
CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or
the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH,"
the BankActivate command is selected and the bank designated by BS is turned on to the
active state. When the WE# is asserted "LOW," the Precharge command is selected and the
bank designated by BS is switched to the idle state after the precharge operation.
Input
Column Address Strobe:
The CAS# signal defines the operation commands in conjunction
with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is
held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS#
"LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."
Input
Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used
to select the BankActivate or Precharge command and Read or Write command.
Input
Data Input/Output Mask:
Controls output buffers in read mode and masks
Input data in write mode.
Input / Output
Data I/O:
The DQ0-15 input and output data are synchronized with the positive edges of
CLK. The I/Os are maskable during Reads and Writes.
-
No Connect:
These pins should be left unconnected.
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V )
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.( 0 V )
Supply
Power Supply:
+3.3V
±
0.3V
Supply
Ground
TM Technology Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
